1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device capable of sequentially selecting memory cell lines and having redundancy. The present invention is particularly applicable to a First-In First-Out (FIFO) memory device.
2. Description of the Background Art
FIFO memory device is well known as a semiconductor memory device having First-In First-Out function (referred to as "FIFO" hereinafter). Stored data in memory cells are read out in the order in which they are written. More specifically, out of the stored data, the oldest is sequentially read out. Accordingly, the FIFO memory device is often used in order to temporarily hold the data to adjust timings in case of data transmission between devices or circuits each having a different processing speed.
FIG. 1 is a block diagram of a conventional FIFO memory device. Referring to FIG. 1, the FIFO memory device comprises a memory cell array 1 having a number of memory cells arranged in matrix of n bits by k rows, a ring pointer circuit 2 for sequentially and repeatedly selecting respective rows of the memory cell array 1, an input driver circuit 3 for supplying input data signals DIl to DIn of n bits to the memory cell array 1, an output driver circuit 4 for reading data signals from the memory cell array 1, and a control circuit 5. One row of the memory cell array 1 comprises n numbers of memory cells. The ring pointer circuit 2 is connected to receive a clock signal .phi. and a reset signal RS generated from the control circuit 5.
In the writing operation, the input data signals DIl to DIn to be written are supplied to the memory cell array 1 through the input driver circuit 3. After being reset by the reset signal RS, the ring pointer circuit 2 sequentially selects each row of the memory cell array 1 in response to the clock signal .phi.. Accordingly, the supplied input data signals DIl to DIn are written in each row selected by the ring pointer circuit 2. Also in the reading operation, the ring pointer circuit 2 sequentially selects each row of the memory cell array 1 in the same manner as in the writing operation. Accordingly, data signals DOl to DOn are read out through the output driver circuit 4 in the order in which they are written. Each row of the memory cell array 1 is selected in response to address signals ADl to ADk outputted from the ring pointer circuit 2.
FIG. 2 is a circuit block diagram of the ring pointer circuit 2 shown in FIG. 1. Referring to FIG. 2, the ring pointer circuit 2 comprises circularly cascaded flip-flops 6, 72 through 7k. Accordingly, the ring pointer circuit 2 having k stages is constituted. Each flip-flop is connected to receive the clock signal .phi. and the reset signal RS outputted from the control circuit 5 shown in FIG. 1. Each of the flip-flops 6, 72 through 7k has a data input terminal 8, a master data output terminal 9, a slave data output terminal 10, a clock input terminal 11 and a reset terminal 12. A slave data output terminal 10 of a flip-flop in a preceding stage is connected to a data input terminal 8 of a flip-flop in a succeeding stage. A slave data output terminal 10 of a flip-flop in the k-th stage is connected to a data input terminal 8 of a flip-flop in the first stage to constitute a ring pointer. Each of the flip-flops 6, 72 through 7k receives the clock signal .phi. and the reset signal RS through the clock input terminal 11 and the reset terminal 12. The flip-flops 6, 72 through 7k output the address signals ADl to ADk through the master data output terminal 9, respectively. The address signals ADl to ADk are supplied to the memory cell array 1, as described above.
FIG. 3 is a circuit diagram of the flip-flop 6 in the first stage shown in FIG. 2. Referring to FIG. 3, the flip-flop 6 comprises NMOS transistors 13 and 14, PMOS transistors 15 and 16, four inverters 17, 18, 19 and 20, a NOR gate 21 and an NAND gate 22. This flip-flop 6 also comprises a master latch 6m and a slave latch 6s.
During the operation, when the reset signal e,ovs/RS/ of a low (logical low) level is supplied, a signal of a high (logical high) level is outputted as a master data output DOm through the terminal 9, irrespective of a level of the clock signal .phi.. On the other hand, when the reset signal RS of a high level is supplied, the flip-flop 6 operates as a general master slave type flip-flop. More specifically, the flip-flop 6 outputs input data DI supplied through the data input terminal 8, through the data output terminal 9, in response to the rise of the clock signal .phi.. In addition, in response to the fall of the clock signal .phi., the master data output DOm is latched in the master latch 6m and supplied to the slave latch 6s. The data signal supplied to the slave latch 6s is outputted as a slave data output DOs through the slave data output terminal 10.
FIG. 4 is a circuit diagram showing one of the flip-flops 72 to 7k. Referring to FIG. 4, this flip-flop 7 comprises NMOS transistors 23 and 24, PMOS transistors 25 and 26, three inverters 27, 28 and 29, and NAND gates 30 and 31. The flip-flop 7 also includes a master latch 7m and a slave latch 7s.
During the operation, when the reset signal e,ovs/RS/ of the low level is supplied, the flip-flop 7 outputs two low level signals through the terminals 9 and 10 as a master data output DOm and a slave data output DOs, respectively irrespective of a level of the clock signal .phi.. On the other hand, when the reset signal e,ovs/RS/ of the high level is supplied, the flip-flop 7 operates as a general master slave type flip-flop. More specifically, the input data DI supplied through the terminal 8 is outputted as the master data output DOm through the terminal 9, in response to the rise of the clock signal .phi.. The master data output DOm is latched in the master latch 7m, in response to the fall of the clock signal .phi.. At the same time, the master data output DOm is supplied to the slave latch 7s and outputted as the slave data output DOs through the terminal 10.
Now, with reference to the timing chart shown in FIG. 5, operation of the ring pointer circuit 2 shown in FIG. 2 will be described. First, in a period P.sub.1, the reset signal e,ovs/RS/ of the low level is supplied through each terminal 12 shown in FIG. 2. Accordingly, only the first flip-flop 6 outputs the address signal ADl of the high level through the terminal 9. On the other hand, the other flip-flops 72 to 7k output the address signals AD2 to ADk of the low level, in response to the reset signals e,ovs/RS/ of the low level.
Then, in a period P.sub.2 and thereafter, the reset signal RS of the high level is supplied. When the clock signal .phi. rises, only the second flip-flop 72 outputs the master data output DOm, that is, the address signal AD2 of the high level through the terminal 9. Other flip-flops than the flip-flop 72 output address signals of the low level. When the clock signal .phi. falls, the master data output DOm of the second flip-flop 72 is latched to the high level.
Furthermore, in a period P.sub.3, only the third flip-flop (not shown) outputs the address signal AD3 of the high level. Through the repetition of the above described operation, the flip-flops 6, 72 through 7k sequentially output the address signals ADl to ADk of the high level.
In a period P.sub.k, in response to a fall of the k-th clock signal .phi., the master data output DOm of the k-th flip-flop 7k is latched to the high level. In response to a subsequent fall of the clock signal .phi., the first flip-flop 6 outputs the master data output DOm of the high level.
Accordingly, so long as no reset signal e,ovs/RS/ of the low level is supplied, the address signals ADl to ADk sequentially and repeatedly attain the high level in response to the clock signal .phi.. As a result, each row of the memory cell array 1 shown in FIG. 1 is sequentially and repeatedly selected.
Meanwhile, in general, a predetermined test is applied to a semiconductor memory devices before shipping in order to detect defects and eliminate the same. In the test, it is detected whether a defective memory cell exists in a memory cell array or not. Also with respect to a FIFO memory device, it is detected whether or not a defective memory cell exists. If a defective memory cell exists in the memory cell array, the FIFO memory device should be treated as defective. The reason is that in a conventional FIFO memory device, it is not possible to avoid selecting a memory cell line having a defective memory cell.